The present invention relates to an architecture and method for locating faults in a memory device. One embodiment of the invention relates to an apparatus and method for testing EPROM-based One Time Programmable (OTP) memories to locate hardware faults in the address input lines, the row or column decoders or certain faults in the memory cell array.
In the manufacture of memory devices, it is typically desired to test the memory devices for faults before delivering or selling the memory devices. One type of memory which is typically tested is read only memory. This is a memory which is designed so that, in normal use, its contents can be read but cannot be written to or changed. A programmable read only memory (PROM) is a memory which can be written to once, i.e., in which it is possible to electronically change the state of a given memory cell (i.e., the unit of memory which is in either a first or second state, storing a "1" or a "0") from its erased state to the opposite state but in which an erasing of the programmed memory cell is not done during normal operation. The writing of data to a cell of the PROM is called "programming". Typically, a PROM cell is programmed using voltages higher than those used in addressing and reading a cell.
One class of PROMs permits erasing of programmed cells but requires special procedures for erasing and thus does not permit erasing during normal, routine use of the memory. These memories are referred to as an erasable programmable read only memories (EPROM). In some types of EPROMs, data programmed or stored in the memory can be erased by exposing the cells to light, typically ultraviolet light. These memories are manufactured in a package which includes a window, typically a quartz window to permit transmission of ultraviolet light. Windowed EPROMs are particularly useful during software development because the memory can be reprogrammed to correct programming errors and the like. One difficulty with windowed EPROMs is the relatively high cost of producing the windowed packages. So it is economically advantageous to substitute windowed EPROMs with windowless EPROMs in products, after the software development phase is completed. These are sometimes referred to as one-time programmable (OTP) EPROMs. This term is something of a misnomer since, being windowless, the memory, once packaged, is not erasable.
OTP EPROMs, while valuable for the reasons discussed above, present certain difficulties in testing the parts after manufacture. This can be best understood by describing how testing of normal or "windowed" EPROMs is conducted. Although a number of testing methodologies for windowed EPROMs are available, the testing used according to previous schemes has involved writing data to at least some of the memory cells in the normally-used array, as described, for example, in M. Pawlowski, et al "Functional Testing of EPROM's", IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 2, April, 1984, pps. 212-218. This presents no particular difficulty in the context of windowed EPROMs since, following such a programming of cells in the array, the EPROM can be erased to permit the desired final program to be placed into the memory array. Even with windowed EPROMs, this procedure has the undesirable characteristic that erasing the arrays can be undesirably time-consuming.
This type of testing is infeasible using cells in the memory array used in normal operation of a packaged OTP device, since these cells if programmed for a testing purpose cannot be thereafter erased to permit insertion of the desired program into memory. Varying degrees of testing capability for OTP EPROMs could be achieved providing additional memory cells (i.e. in addition to those which are accessed during normal use of the device). For example, in many commercially available OTP EPROMs, a certain number of additional cells are provided, in addition to the normal array, exclusively for the purpose of testing certain functions. However, this approach has the disadvantage that it increases the silicon area requirement. Furthermore, this type of testing is non-repeatable with a same set of test cells, if test procedures involve programming the test cells each time, since they cannot be erased in a packaged OTP EPROM. Designs permitting single fault coverage in packaged OTP EPROMs for faults in addressing logic, including address inputs, in repeatable manner, (with tests involving a write to memory cells, at least a first time), if at all possible, will consume silicon area, adversely affecting the economic feasibility of the commercial product. Economic implementation of repeatable tests would be advantageous in the production environment, customer testing, testing of customer-returned parts, and testing at different stages (for example, after dynamic burn-in).
Accordingly, it would be useful to provide an OTP EPROM which can be tested so as to detect different types of address line and decoder faults as well as most of the memory cell array faults not involving charge storage. It would also be useful to provide an OTP EPROM in which this fault testing can be repeatable.